1. Field of the Invention
The current invention generally relates to semiconductor products. More specifically, the present invention relates to making body contacts on FinFETs.
2. Description of the Related Art
Field Effect Transistors (FETs) have been the dominant semiconductor technology used to make Application Specific Integrated Circuit (ASIC) chips, microprocessor chips, Static Random Access Memory (SRAM) chips, and the like for many years. In particular, Complementary Metal Oxide Semiconductor (CMOS) technology has dominated the semiconductor process industry for a number of years.
Technology advances have scaled FETs on semiconductor chips to increasingly small dimensions, allowing power per logic gate to be dramatically reduced, and further allowing a very large number of FETs to be fabricated on a single semiconductor chip. Scaling of FETs is currently running into physical limits. Gate oxides have become thin enough that leakage occurs through the gate oxides. Further scaling of gate oxide thickness will bring an exponential increase in leakage. Power dissipated by leakage currents has become a significant portion of total chip power, and an exponential increase in leakage results in unacceptable power dissipation for many types of chips.
Silicon on Insulator (SOI) processes have reduced FET source and drain capacitances, resulting in an improved power/performance ratio for CMOS chips fabricated in an SOI process. However, conventional SOI processes are reaching fundamental limits, resulting in undesirable effects such as the leakage effects mentioned above. Therefore, innovative new ways to make CMOS devices are being created. A FinFET is a recently developed FET device that utilizes 3-D (three dimensional) techniques to pack a large number of FETs in a given area of a semiconductor chip while reducing some of the problems described above.
Prior art FIG. 1 shows an isometric view of a FinFET. A tall, thin semiconductor fin 2 of semiconductor material (typically silicon) suitable for doping as source and drain regions rises from an insulator 1. Polysilicon gate 5 is a polysilicon conductor that surrounds fin 2 on three sides in FIG. 1. In regions where the silicon material is doped P−, source 3 and drain 4 are subsequently doped to become N+ regions, with the P− region under gate 5 serving as a body (not shown in FIG. 1) of the FinFET. A thin gate oxide 6 separates polysilicon gate 5 from the body. FinFETs have significant advantages, being “three dimensional” FETs, the gate can induce conducting channels on three sides, increasing current flow through a conducting FET, and making it less necessary that the gate oxide 6 be as thin as the gate oxide of a conventional planar FET.
FIG. 2A is a prior art drawing showing a top view (i.e., looking “down” towards insulator 1) of a FinFET. Source 3 and drain 4 are doped N+ (for an N-channel FET, an NFET). To better illustrate the makeup of the FinFET, a cross sectional view at AA is shown in FIG. 2B, also prior art. A body 8 is the portion of fin 2 that is the body of the FinFET, and is P− for the NFET. (A P-channel FET (PFET) would begin with an N− doped fin, the source and drain regions of the PFET subsequently doped P+.) The thin gate oxide 6 is shown covering both sides and the top of body 8. Polysilicon gate 5 is the gate of the FinFET and surrounds body 8 on both vertical sides and the top, separated from body 8 by thin gate oxide 6. When polysilicon gate 5 turns on the FinFET (e.g., is a high voltage relative to source 3 for an NFET), carriers conduct from source 3 to drain 4 in a direction into (or out of) the page, in FIG. 2B, in portions of body 8 near thin oxide 6.
One will note in FIG. 2B that body 8 is totally surrounded by insulating material. Insulator 1 is at the bottom of body 8; thin gate oxide 6 surrounds the left, right, and top sides of body 8. Therefore, no electrical connection to body 8 can be made to control a voltage on body 8, other than the P−/N+ junctions (for an NFET) between body 8 and source 3 and drain 4. The body voltage, relative to a voltage on the source of the FET, tends to “float”. For example, when the FET is “off”, and source to drain voltage is relatively high, junction leakage from the drain charges the body. However, if the body voltage becomes more than a diode drop difference from the source voltage, the body/source junction will begin to forward bias, clamping the body voltage to be no more than a diode drop different than the source voltage. (For silicon, diode drops are approximately 0.7 volts). Actual body voltage relative to the source depends on a number of factors, including temperature and switching history of the FET. A threshold voltage of a FET is dependent in part on a voltage difference between the source and the body. Many digital applications (e.g., NAND gates, NOR gates, latches, and the like) are not greatly affected by threshold uncertainty caused by variation of body to source voltage variation that can occur. For example, small delay uncertainties may occur that are acceptable, and accounted for in delay calculations. However, a number of circuits rely on a known source to body voltage for proper operation. Examples of such circuits that rely on a known source to body voltage for proper operation include, but not limited to, differential receivers, operational amplifiers, and the like. Such circuits that rely on known source to body voltages require that the body be tied to a voltage. Often, NFET bodies are coupled to ground; PFET bodies are tied to a positive supply often referred to as Vdd. Often, FETs, used in a differential stage having gates coupled to a true and a complement signal, have bodies coupled together.
Therefore, there is a need for a method and apparatus that create a FinFET body contact so that the FinFET body can be coupled to a voltage supply, or to other FinFET bodies.